A delay model and optimization method of a low-power BiCMOS logic circuit.

Shayan Zhang T. S. Kalkur Steven Lee Lori Gatza

Published in: IEEE J. Solid State Circuits (1994)

Keyphrases

optimization method
low power
high speed
optimization process
low cost
optimization algorithm
power consumption
logic circuits
probabilistic model
optimization methods
delay insensitive
neural network
image processing
maximum likelihood