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An Accurate Worst Case Timing Analysis Technique for RISC Processors.
Sung-Soo Lim
Young Hyun Bae
Gyu Tae Jang
Byung-Do Rhee
Sang Lyul Min
Chang Yun Park
Heonshik Shin
Kunsoo Park
Chong-Sang Kim
Published in:
RTSS (1994)
Keyphrases
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worst case
instruction set
high accuracy
lower bound
upper bound
application specific
average case
parallel algorithm
highly accurate
greedy algorithm
multi agent
floating point
parallel processing
error bounds
space complexity
computationally efficient
np hard
general purpose
high end
parallel processors
multi class