26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique.
Hyeok-Ki HongHyun-Wook KangDong-Shin JoDong-Suk LeeYong-Sang YouYong-Hee LeeHo-Jin ParkSeung-Tak RyuPublished in: ISSCC (2015)
Keyphrases
- hardware architecture
- real time
- hardware implementation
- low cost
- hardware software
- vlsi implementation
- software implementation
- hardware design
- vlsi architecture
- hardware and software
- dedicated hardware
- management system
- pipeline architecture
- hardware architectures
- power consumption
- single chip
- reconfigurable hardware
- commercial off the shelf
- content addressable
- sigma delta
- analog to digital converter
- parallel architecture
- massively parallel
- parameter estimation
- computer systems
- image processing
- image sensor
- field programmable gate array
- power plant
- data flow
- host computer
- fpga technology
- signal processing