26.4 A 0.4-to-1V 1MHz-to-2GHz switched-capacitor adiabatic clock driver achieving 55.6% clock power reduction.

Loai G. Salem Patrick P. Mercier

Published in: ISSCC (2017)

Keyphrases

power consumption
power reduction
high speed
clock frequency
clock gating
low power
power saving
energy efficiency
cmos technology
image processing
computer systems
wireless networks
frequency band