Novel low-power and stable memory cell design using hybrid CMOS and MTJ.
Govind PrasadDeeksha SahuBipin Chandra MandiMaifuz AliPublished in: Int. J. Circuit Theory Appl. (2022)
Keyphrases
- low power
- single chip
- power consumption
- power dissipation
- low cost
- high speed
- cmos technology
- low power consumption
- vlsi architecture
- logic circuits
- mixed signal
- nm technology
- vlsi circuits
- digital signal processing
- analog to digital converter
- high power
- ultra low power
- gate array
- wireless transmission
- cmos image sensor
- power reduction
- real time
- image sensor
- delay insensitive
- design process
- low voltage
- power saving