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Reducing cache and TLB power by exploiting memory region and privilege level semantics.
Zhen Fang
Li Zhao
Xiaowei Jiang
Shih-Lien Lu
Ravi R. Iyer
Tong Li
Seung Eun Lee
Published in:
J. Syst. Archit. (2013)
Keyphrases
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cache misses
memory subsystem
multithreading
main memory
power consumption
memory access
memory hierarchy
input image
region of interest
read write
knowledge base
query processing
logic programming
image regions
prefetching
secondary storage