Low Power 16 x 16 Bit Multiplier Design Using PAL-2N Logic Family.
H. H. WongK. T. LauPublished in: J. Circuits Syst. Comput. (2002)
Keyphrases
- low power
- logic circuits
- single chip
- power consumption
- low cost
- high speed
- low power consumption
- vlsi architecture
- mixed signal
- digital signal processing
- real time
- delay insensitive
- high power
- power dissipation
- nm technology
- analog to digital converter
- gate array
- cmos image sensor
- ultra low power
- cmos technology
- power reduction
- floating point
- embedded systems
- design process
- general purpose