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Scalable dual-instruction multiple-data processing on an efficient systolic-array architecture.
Yuxi Tan
Riadh Ben Abdelhamid
Bingjie Guo
Qixiang Gao
Masaru Nishimura
Yoshiki Yamaguchi
Published in:
IPDPS (Workshops) (2024)
Keyphrases
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systolic array
data processing
parallel architecture
data flow
reconfigurable architecture
computer systems
data analysis
data management
dynamic programming
distributed memory
instruction set
scalable distributed
level parallelism