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Reducing the overall cache miss rate using different cache sizes for Heterogeneous Multi-core Processors.

Bruno de Abreu SilvaLucas Albers CuminatoVanderlei Bonato
Published in: ReConFig (2012)
Keyphrases
  • miss rate
  • multi core processors
  • multithreading
  • prefetching
  • cache misses
  • general purpose
  • data structure
  • main memory
  • data access
  • databases
  • low cost
  • parallel processing
  • replacement policy