Stretching the capacity of Hardware Transactional Memory in IBM POWER architectures.
Ricardo FilipeShady IssaPaolo RomanoJoão BarretoPublished in: CoRR (2020)
Keyphrases
- parallel architectures
- transactional memory
- speculative execution
- blue gene
- massively parallel
- computing systems
- commodity hardware
- field programmable gate array
- parallel computing
- hardware design
- low cost
- parallel execution
- parallel processing
- high end
- image processing
- highly parallel
- efficient implementation
- hardware and software
- computer systems
- parallel programming
- hardware implementation
- address space
- parallel computers
- data analytics
- real time
- embedded systems
- shared memory