Low power design of H.264 CAVLC decoder.

Heng-Yao Lin Ying-Hong Lu Bin-Da Liu Jar-Ferr Yang

Published in: ISCAS (2006)

Keyphrases

low power
single chip
high speed
low cost
logic circuits
low power consumption
power consumption
vlsi architecture
power dissipation
mixed signal
cmos technology
low complexity
digital signal processing
power reduction
gate array
vlsi circuits
ultra low power
wireless transmission