A two-step folder for a high-speed CMOS folding-and-interpolating ADC.

Sang Chan Han Bum Soo Suh Soo Won Kim

Published in: ICECS (2001)

Keyphrases

high speed
low power
post processing
real time
frame rate
single chip
focal plane
learning algorithm
low cost
infrared
power consumption
circuit design
protein folding
data sets
fine grained
image sensor