A novel power noise simulation methodology for chip design using Wafer Level Chip Scale Packaging.

Yipin Wu Zhigang Hao Jingchun Han Joy Tsai

Published in: VLSI-DAT (2014)

Keyphrases

database systems
chip design
design methodology
physical design
design process
power dissipation
high speed
low cost
real time
power consumption
field effect transistors
relational databases
fuzzy neural network
semiconductor manufacturing