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A 5 dBm 30.6% Efficiency 915 MHz Transmitter with $210\ \mu \mathrm{W}$ ULP PLL Employing Frequency Tripler and Digitally Controlled Duty/Phase Calibration Buffer.
Kyung-Sik Choi
Keun-Mok Kim
Jinho Ko
Sang-Gug Lee
Published in:
A-SSCC (2020)
Keyphrases
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camera calibration
phase difference
high speed
communication systems
development environment
neural network
clock frequency
radially symmetric