On the hardware implementation efficiency of SHA-3 candidates.
Paris KitsosNicolas SklavosPublished in: ICECS (2010)
Keyphrases
- hardware implementation
- efficient implementation
- signal processing
- hardware design
- dedicated hardware
- fpga implementation
- software implementation
- image processing algorithms
- field programmable gate array
- image binarization
- parallel architecture
- pipeline architecture
- memory management
- hardware architecture
- computational complexity
- operating system
- high speed
- data streams
- image processing