A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop.

Li Zhang Baoyong Chi Zhihua Wang Hongyi Chen Jinke Yao Ende Wu

Published in: ISCAS (2007)

Keyphrases

phase locked loop
high speed
power consumption
low cost
analog vlsi
low power
image sensor
power supply
delay insensitive
real time
frequency band