A Low-Phase Noise ADPLL Based on a PRBS-Dithered DDS Enhancement Circuit.

Noura Ben Ameur

Published in: J. Circuits Syst. Comput. (2017)

Keyphrases

phase locked loop
user friendly
high speed
image enhancement
analog circuits
low cost
high levels
frequency response
analog vlsi
neural network
evolutionary algorithm
evolvable hardware
delay insensitive