A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS.
Hanli LiuZheng SunHongye HuangWei DengTeerachot SiriburanonJian PangYun WangRui WuTeruki SomeyaAtsushi ShiraneKenichi OkadaPublished in: ISSCC (2019)
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