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A self-reconfigurable hardware architecture for mesh arrays using single/double vertical track switches.
Masaru Fukushi
Susumu Horiguchi
Published in:
IEEE Trans. Instrum. Meas. (2004)
Keyphrases
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massively parallel
hardware architecture
processing elements
field programmable gate array
hardware implementation
hardware architectures
neural network
image processing
feature extraction
pattern recognition
pairwise
high speed
robotic systems