A Highly Parallel FPGA Implementation of Sparse Neural Network Training.
Sourya DeyDiandian ChenZongyang LiSouvik KunduKuan-Wen HuangKeith M. ChuggPeter A. BeerelPublished in: ReConFig (2018)
Keyphrases
- highly parallel
- fpga implementation
- neural network training
- hardware implementation
- efficient implementation
- neural network
- training algorithm
- parallel architectures
- field programmable gate array
- computing systems
- single chip
- single pass
- optimization method
- image processing algorithms
- general purpose
- parallel programming
- image processing
- particle swarm optimisation
- artificial intelligence
- parallel processing
- back propagation
- graphics processing units
- pattern recognition
- genetic algorithm