A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET.
Stevo BaileyJaeduk HanPaul RiggeRichard LinEric ChangHoward MaoZhongkai WangChick MarkleyAdam M. IzraelevitzAngie WangNathan NarevskyWoo-Rham BaeSteve ShauckSergio MontanoJustin NorsworthyMunir RazzaqueWen Hau MaAkalu LentiroMatthew DoerfleinDarin HeckendornJim McGrathFranco DeSetaRonen ShohamMike StellfoxMark SnowdenJoseph ColeDan FuhrmanBrian C. RichardsJonathan BachrachElad AlonBorivoje NikolicPublished in: A-SSCC (2018)