Area Optimized Synthesis of Compressor Trees on Xilinx FPGAs Using Generalized Parallel Counters.
Yuelai YuanLe TuKan HuangXiaoqiang ZhangTiejun ZhangDihu ChenZixin WangPublished in: IEEE Access (2019)
Keyphrases
- field programmable gate array
- hardware implementation
- parallel computing
- fpga implementation
- high speed
- decision trees
- pipelined architecture
- parallel implementation
- parallel architectures
- parallel processing
- parallel execution
- embedded systems
- programmable logic
- massively parallel
- computer architecture
- tree structures
- processing elements
- hardware architecture
- floating point
- parallel programming
- parallel computation
- real time
- computing systems
- image processing
- genetic algorithm
- machine learning
- neural network