Timing-Optimized Hardware Implementation to Accelerate Polynomial Multiplication in the NTRU Algorithm.
Eros Camacho-RuizSantiago Sánchez-SolanoPiedad BroxMacarena C. Martínez-RodríguezPublished in: ACM J. Emerg. Technol. Comput. Syst. (2021)
Keyphrases
- hardware implementation
- image processing algorithms
- detection algorithm
- learning algorithm
- computational complexity
- optimal solution
- k means
- dynamic programming
- fpga implementation
- objective function
- signal processing
- pipelined architecture
- pipeline architecture
- hardware architecture
- parallel implementation
- efficient implementation
- document images
- real time
- np hard
- face recognition
- image processing
- machine learning