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Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear Pairings.
Cuautëmoc Chävez Corona
Edgar Ferrer Moreno
Francisco Rodríguez-Henríquez
Published in:
ReConFig (2011)
Keyphrases
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hardware design
hardware implementation
bilinear pairings
fpga hardware
field programmable gate array
computer vision
lightweight
efficient implementation
floating point
signature scheme
threshold signature scheme
identity based cryptography