A Survey of Low Power Design Techniques for Last Level Caches.
Emmanuel Ofori-AttahXiaohang WangMichael Opoku AgyemanPublished in: ARC (2018)
Keyphrases
- low power
- single chip
- low power consumption
- power consumption
- low cost
- high speed
- gate array
- logic circuits
- vlsi architecture
- power dissipation
- digital signal processing
- power reduction
- ultra low power
- mixed signal
- cmos technology
- vlsi implementation
- wireless transmission
- design methodology
- vlsi circuits
- efficient implementation