Designing low power magentic flip flop in 45 nm FDSOI technology for large scale cluster based engineering application.
K. SakthimuruganK. GeethaPublished in: Clust. Comput. (2019)
Keyphrases
- low power
- cmos technology
- power consumption
- high speed
- low cost
- nm technology
- power dissipation
- wireless transmission
- gate array
- single chip
- low voltage
- flip flops
- ultra low power
- vlsi circuits
- parallel processing
- low power consumption
- vlsi architecture
- logic circuits
- mixed signal
- digital signal processing
- high power
- digital images