New ASIC/FPGA Cost Estimates for SHA-1 Collisions.
Muhammad HassanAyesha KhalidAnupam ChattopadhyayChristian RechbergerTim GüneysuChristof PaarPublished in: DSD (2015)
Keyphrases
- hardware implementation
- hardware architecture
- single chip
- xilinx virtex
- high speed
- high cost
- low cost
- total cost
- application specific
- integrated circuit
- cost sensitive
- field programmable gate array
- signal processing
- cost reduction
- dedicated hardware
- low power
- hash functions
- minimum cost
- hardware design
- parallel processing
- software implementation
- database