VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes.
Yang SunMarjan KarkootiJoseph R. CavallaroPublished in: ISCAS (2007)
Keyphrases
- high throughput
- ldpc codes
- rate allocation
- decoding algorithm
- error correction
- microarray
- message passing
- low density parity check
- rate distortion
- video coding
- bitstream
- source coding
- channel coding
- coding efficiency
- data acquisition
- real time
- video coding standard
- video transmission
- motion estimation
- macroblock
- bit plane
- distributed video coding
- bit rate
- intra prediction
- low complexity
- coding scheme
- error concealment
- motion compensated
- motion compensation
- high speed