A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range.

Adnan Gundel William N. Carr

Published in: ISCAS (2007)

Keyphrases

low voltage
cmos technology
power consumption
low power
high speed
wide range
parallel processing
concurrency control
end to end delay
database systems
wireless sensor networks
low cost
image quality
packet loss
high levels
nm technology