A High Level Synthesis Methodology for Dynamic Monitoring of FPGA ML Accelerators.
Ryan F. ForelliRui ShiSeda OgrenciJoshua AgarPublished in: VTS (2024)
Keyphrases
- high level synthesis
- field programmable gate array
- real time
- parallel architecture
- monitoring system
- maximum likelihood
- single chip
- high speed
- hardware implementation
- signal processing
- dynamic environments
- data acquisition
- probabilistic model
- low cost
- scheduling problem
- computing systems
- pairwise
- image segmentation
- case study