VLSI architectures for high speed and low power implementation of 5/3 lifting discrete wavelet transform.
Usha Bhanu NageswaranA. ChilambuchelvanPublished in: Int. J. Comput. Sci. Eng. (2016)
Keyphrases
- low power
- high speed
- discrete wavelet transform
- vlsi architecture
- lifting scheme
- single chip
- wavelet domain
- cmos technology
- multiresolution
- vlsi circuits
- high frequency
- wavelet coefficients
- wavelet transform
- subband
- low cost
- power consumption
- gate array
- digital signal processing
- low frequency
- logic circuits
- image fusion
- real time
- ultra low power
- frame rate
- integer wavelet transform
- wavelet filters
- power dissipation
- feature vectors
- spatial domain
- image sensor
- human visual system
- image compression
- digital images
- image analysis
- computational complexity
- mixed signal
- pattern recognition
- similarity measure
- feature extraction