A 223Mbps FPGA Implementation of (10240, 5120) Irregular Structured Low Density Parity Check Decoder.
Wenjun WangXiaoguang WuXiaoxuan ZhuGuixia KangXiaofeng TaoPublished in: VTC Spring (2008)
Keyphrases
- fpga implementation
- low density parity check
- ldpc codes
- vlsi architecture
- hardware implementation
- decoding algorithm
- distributed video coding
- channel coding
- error correction
- field programmable gate array
- low complexity
- low power
- message passing
- image processing algorithms
- real time
- physical layer
- transfer function
- error resilient
- efficient implementation
- channel capacity