VLSI Architecture of Arithmetic Coder Used in SPIHT.
Kai LiuEvgeniy BelyaevJie GuoPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2012)
Keyphrases
- vlsi architecture
- arithmetic coder
- bit plane
- low complexity
- coding scheme
- compression algorithm
- vlsi implementation
- low power
- bitstream
- image coding
- mode decision
- coding method
- real time
- image compression
- distributed video coding
- motion estimation
- image coder
- data compression
- transform domain
- probability model
- computational complexity
- video streaming
- compression ratio
- entropy coding
- compression scheme
- lossless compression
- rate distortion
- low cost
- wavelet coefficients
- computationally efficient
- arithmetic coding
- high speed
- multiscale