A high performance reconfigurable parallel processing architecture.
Richard R. ShivelyE. B. MorganT. W. CopleyAllen L. GorinPublished in: SC (1989)
Keyphrases
- parallel processing
- parallel computers
- distributed processing
- ibm sp
- parallel architecture
- pc cluster
- computational power
- systolic array
- processing units
- processing speed
- hardware implementation
- compute intensive
- parallel architectures
- low cost
- parallel computation
- processing elements
- tree decomposition
- dynamic reconfiguration
- real time
- graphics processing units
- image processing algorithms
- computation intensive
- parallel programming
- reconfigurable hardware
- software architecture
- cmos image sensor