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Multi-port abstraction layer for FPGA intensive memory exploitation applications.

Mauricio VanegasMatteo TomasiJavier DíazEduardo Ros Vidal
Published in: J. Syst. Archit. (2010)
Keyphrases
  • abstraction layer
  • memory requirements
  • high speed
  • memory usage
  • hardware implementation
  • memory management
  • image processing
  • real time image processing
  • real time
  • signal processing
  • memory size
  • pipelined architecture