The Saga of Synchronous Bus Arbiter: On Model Checking Quantitative Timing Properties of Synchronous Programs.
Paritosh K. PandyaPublished in: Electron. Notes Theor. Comput. Sci. (2002)
Keyphrases
- model checking
- temporal properties
- temporal logic
- asynchronous circuits
- finite state machines
- timed automata
- formal specification
- formal verification
- verification method
- model checker
- finite state
- automated verification
- reachability analysis
- formal methods
- computation tree logic
- bounded model checking
- process algebra
- epistemic logic
- partial order reduction
- concurrent systems
- transition systems
- symbolic model checking
- abstract interpretation
- linear temporal logic
- satisfiability problem
- software architecture
- np complete
- deterministic finite automaton
- reactive systems
- pspace complete