A 1.5pJ/bit, 5-to-10Gbps Forwarded-Clock I/O with Per-Lane Clock De-Skew in a Low Power 28nm CMOS Process.
Anup JoseValentin AbramzonMohamed ElzeftawiMichael WangKyunglok KimYounghoon SongShiva MoballeghJalil KamaliAmir AmirkhanyPublished in: CICC (2019)
Keyphrases
- low power
- power consumption
- high speed
- nm technology
- cmos technology
- power saving
- low cost
- logic circuits
- power reduction
- high power
- single chip
- digital signal processing
- power management
- vlsi architecture
- low power consumption
- image sensor
- power dissipation
- wireless transmission
- delay insensitive
- traffic flow
- gate array