Low power and high speed multiplier design with row bypassing and parallel architecture.
Ko-Chi KuoChi-Wen ChouPublished in: Microelectron. J. (2010)
Keyphrases
- low power
- high speed
- single chip
- low power consumption
- low cost
- vlsi architecture
- power consumption
- logic circuits
- digital signal processing
- parallel architecture
- gate array
- cmos technology
- high level synthesis
- power dissipation
- mixed signal
- vlsi circuits
- high power
- power reduction
- real time
- ultra low power
- hardware implementation
- nm technology
- design process
- systolic array
- efficient implementation
- probabilistic model