Taking advantage of optimal on-chip parallelism for parallel discrete-event simulation.
Jack V. Briner Jr.John L. EllisGershon KedemPublished in: ICCAD (1988)
Keyphrases
- discrete event simulation
- level parallelism
- parallel processing
- shared memory
- massively parallel
- parallel computing
- parallel computation
- optimal solution
- data parallelism
- parallel execution
- low cost
- parallel programming
- distributed memory
- discrete event
- parallel computers
- multithreading
- high speed
- parallel architectures
- semiconductor manufacturing
- supply chain
- parallel implementation
- worst case
- evolutionary algorithm
- real time
- memory bandwidth