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Minimize the delay of parasitic capacitance and modeling in RLC circuit.

Dukgwon LeeSeunghyun BeakYoungmin LeeEunser LeeJungkook KimGyung-Leen ParkTaikyeong Jeong
Published in: ICHIT (2009)
Keyphrases
  • high speed
  • power dissipation
  • low power
  • data sets
  • neural network
  • machine learning
  • artificial neural networks
  • multiresolution
  • modeling framework
  • circuit design
  • delay insensitive