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SHA-3 Instruction Set Extension for A 32-bit RISC processor architecture.
Ahmed S. Eissa
Mahmoud A. Elmohr
Mostafa A. Saleh
Khaled E. Ahmed
Mohammed M. Farag
Published in:
ASAP (2016)
Keyphrases
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instruction set
instruction set architecture
floating point
application specific
computer architecture
embedded systems
level parallelism
ibm power processor
low cost
memory access
artificial intelligence
information systems
general purpose
sufficient conditions
database applications
memory subsystem