A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC.

Ting Li Dongbing Fu Yong Zhang Yan Wang Lu Liu Xu Wang

Published in: ASICON (2013)

Keyphrases

high speed
shift register
analog to digital converter
low power
back end
mixed signal
real time
frame rate
single chip
focal plane
high speed networks
logic circuits
data sets
wide dynamic range
instruction set architecture
random number generator
random access memory
cmos technology
parallel architecture
data flow