Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines.
Chris R. JesshopePublished in: ACSAC (2001)
Keyphrases
- multi processor
- instruction set
- level parallelism
- ibm power processor
- multi core processors
- shared memory
- memory access
- multithreading
- memory subsystem
- program execution
- single processor
- floating point
- distributed memory
- computer architecture
- low cost
- parallel programming
- application specific
- highly efficient
- embedded systems
- memory efficient
- memory management
- parallel computing
- parallel algorithm
- operating system
- data processing