A new gate-level body biasing technique for PMOS transistors in subthreshold CMOS circuits.
Walid ElgharbawyPradeep GolcondaAshok KumarMagdy A. BayoumiPublished in: ISCAS (5) (2005)
Keyphrases
- cmos technology
- floating gate
- low voltage
- low power
- circuit design
- power consumption
- field effect transistors
- high speed
- power dissipation
- parallel processing
- focal plane
- image sensor
- levels of abstraction
- delay insensitive
- data sets
- flip flops
- random access memory
- steady state
- markov chain
- low cost
- vlsi circuits
- chip design
- silicon on insulator
- single chip
- metal oxide semiconductor
- higher level
- image sequences
- image processing