Predicate Abstraction and Refinement for Model Checking VHDL State Machines.
Mustapha BourahlaMohamed BenmohamedPublished in: Electron. Notes Theor. Comput. Sci. (2002)
Keyphrases
- model checking
- state machines
- state machine
- reactive systems
- bounded model checking
- finite state machines
- temporal logic
- formal verification
- petri net
- model checker
- formal specification
- automated verification
- verification method
- temporal properties
- symbolic model checking
- recurrent networks
- high level
- sequence diagrams
- epistemic logic
- timed automata
- transition systems
- linear temporal logic
- computation tree logic
- formal methods
- concurrent systems
- neural network
- planning domains
- first order logic
- decision theoretic planning
- state space