A multiple clocking scheme for low-power RTL design.
Christos A. PapachristouMehrdad NouraniMark SpiningPublished in: IEEE Trans. Very Large Scale Integr. Syst. (1999)
Keyphrases
- low power
- single chip
- power consumption
- low cost
- high speed
- power dissipation
- vlsi architecture
- logic circuits
- low power consumption
- circuit design
- digital signal processing
- design process
- mixed signal
- wireless transmission
- vlsi circuits
- gate array
- cmos technology
- nm technology
- embedded systems
- image processing
- high power