Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era.
João AndradeFrederico PratasGabriel FalcãoVítor Manuel Mendes da SilvaLeonel SousaPublished in: ASAP (2014)
Keyphrases
- low density parity check
- low power
- ldpc codes
- decoding algorithm
- error correction
- low cost
- power consumption
- high speed
- channel coding
- low complexity
- vlsi architecture
- single chip
- distributed video coding
- physical layer
- digital signal processing
- error resilience
- low power consumption
- logic circuits
- image sensor
- design methodology
- message passing
- real time
- packet loss
- signal processing
- motion estimation