A flexible VLSI architecture of transport processor for an AVS HDTV decoder SoC.
Zhenrui ZhangDi WuPeng ZhangDon XieWen GaoPublished in: IEEE Trans. Consumer Electron. (2006)
Keyphrases
- vlsi architecture
- low complexity
- low power
- high speed
- vlsi implementation
- motion estimation
- low density parity check
- computational complexity
- distributed video coding
- power consumption
- video codec
- low cost
- video coding standard
- real time
- video streaming
- error concealment
- video conferencing
- inter frame
- high definition
- mode decision
- video decoder