Area-efficient and high-speed hardware structure of hybrid cryptosystem (AES-RC4) for maximizing key lifetime using parallel subpipeline architecture.
Senthil Murugan ManiamT. SasilathaPublished in: Concurr. Comput. Pract. Exp. (2021)
Keyphrases
- high speed
- parallel architectures
- real time
- processing elements
- hardware architecture
- parallel architecture
- hardware and software
- master slave
- parallel hardware
- parallel processing
- vlsi architecture
- hardware implementation
- multithreading
- private key
- content addressable memory
- multi core processors
- parallel execution
- computer architecture
- parallel computation
- processing units
- massively parallel
- efficient implementation
- cellular automata
- advanced encryption standard
- public key cryptosystem
- wireless sensor networks