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Design of Tunnel Junction Engineered Dopingless TFET for Low power Applications.
Abhishek Verma
Suruchi Sharma
Sneha Bharti
Manisha Bharti
Baljit Kaur
Published in:
ISDCS (2020)
Keyphrases
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low power
high speed
low cost
single chip
low power consumption
power consumption
vlsi architecture
logic circuits
power reduction
digital signal processing
gate array
cmos technology
power dissipation
design process
mixed signal
ultra low power
real time
cmos image sensor
image processing